cic_tx

2018.05.31.21:56:29 Datasheet
Overview

Memory Map

cic_ii_0

altera_cic_ii v17.1


Parameters

design_env NATIVE
selected_device_family CYCLONEIVE
FILTER_TYPE interpolator
STAGES 6
D_DELAY 1
VRC_EN 0
RCF_FIX 250
RCF_LB 8
RCF_UB 21
RCF_MIN 250
RCF_MAX 250
INTERFACES 1
CH_PER_INT 1
IN_WIDTH 24
CLK_EN_PORT false
ROUND_TYPE CONV_ROUND
REQ_OUT_WIDTH 12
OUT_WIDTH 12
INT_USE_MEM false
INT_MEM auto
REQ_INT_MEM logic_element
DIF_USE_MEM false
DIF_MEM auto
REQ_DIF_MEM logic_element
REQ_PIPELINE 0
PIPELINING 0
C_STAGE_0_WIDTH 64
I_STAGE_0_WIDTH 64
C_STAGE_1_WIDTH 64
I_STAGE_1_WIDTH 64
C_STAGE_2_WIDTH 64
I_STAGE_2_WIDTH 64
C_STAGE_3_WIDTH 64
I_STAGE_3_WIDTH 64
C_STAGE_4_WIDTH 64
I_STAGE_4_WIDTH 64
C_STAGE_5_WIDTH 64
I_STAGE_5_WIDTH 64
C_STAGE_6_WIDTH 64
I_STAGE_6_WIDTH 64
C_STAGE_7_WIDTH 64
I_STAGE_7_WIDTH 64
C_STAGE_8_WIDTH 64
I_STAGE_8_WIDTH 64
C_STAGE_9_WIDTH 64
I_STAGE_9_WIDTH 64
C_STAGE_10_WIDTH 64
I_STAGE_10_WIDTH 64
C_STAGE_11_WIDTH 64
I_STAGE_11_WIDTH 64
MAX_I_STAGE_WIDTH 64
MAX_C_STAGE_WIDTH 64
hyper_opt_select 0
hyper_opt 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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